1. Field of the Invention
This invention relates generally to an inverter circuit and in particular to an improved inverter circuit capable of providing highly stable output signals. The present invention has a particular applicability to a buffer circuit for integrated circuit devices.
2. Description of the Prior Art
Referring to FIG. 1, a typical prior art semiconductor integrated circuit device (hereinafter referred to as a IC device) is shown connected to a device for testing the same. Specifically, the IC device 10 to be tested is connected to an IC tester 30 via a performance board 20. The IC device includes an input buffer 11 for receiving test data signals and test enable signals T.sub.E from the IC tester 30, an inner circuit 13 for processing test data, and an output buffer 12 for transferring signals from the inner circuit 13 as outputs. The IC tester 30 contains a comparator circuit 32 to be connected to the IC device to receive outputs signals therefrom representing the test results, and a DC source 33. Supply voltage V.sub.DD from the DC source 33 is applied to the IC device 10 through the performance board 20.
In FIG. 2, there is illustrated a prior art output buffer circuit for the IC device which comprises a pair of inverters. The output buffer circuit 12 includes CMOS inverters I.sub.1 and I.sub.2. One inverter I.sub.1 comprises a P-channel MOS field effect transistor (hereinafter referred to as FET) 1 and a N-channel MOSFET 2 which are connected in series between the supply voltage V.sub.DD and ground potential GND. The FETs 1 and 2 have their gates connected together to receive input voltage signals V.sub.IN. The other inverter I.sub.2 also includes a P-channel MOSFET 3 and a N-channel MOSFET 4. The gates of the MOSFETs 3 and 4 are conencted to a junction node N.sub.1 between FETs 1 and 2. A junction node N.sub.2 between the FETs 3 and 4 constitutes an output terminal for the output buffer circuit from which output voltage signals V.sub.OUT are supplied.
In FIG. 3, there is illustrated a timing diagram for input and output voltage signals associated with the output buffer circuit 12. In operation, when the input voltage V.sub.IN changes from a low "L" level to a high "H" level at a time t.sub.1, the high level voltage "H" is applied to the gates of the FETs 1 and 2, thereby rendering the FET 1 non-conductive and the FET 2 conductive. As a result, the high level voltage V.sub.3 at the node N.sub.1 starts falling off upon the lapse of the delay time provided by the CMOS inverter I.sub.1 after time t.sub.1, and it settles down to the "L" level through a predetermined time interval. As the voltage V.sub.3 on the node N.sub.1 drops to the "L" level, the FET 3 is driven conductive, while the FET 4 is driven non-conductive. Consequently, the low level output voltage V.sub.OUT at the node N.sub.2 starts to rise upon the lapse of the delay time provide by the CMOS inverter I.sub.2 after the voltage V.sub.3 at the node N.sub.1 has dropped to the "L" level, and at time t.sub.3 the output signal V.sub.OUT reaches the "H" level.
When the input signal V.sub.IN shifts from the "H" level down to the "L" level at t.sub.4, the FET 1 is turned on while the FET 2 is turned off. Then the voltage V.sub.3 at the node N.sub.1 begins rising upon the passage of the delay time defined by the CMOS inverter after t.sub.4, and it reaches the "H" level through a predetermined time. Upon the voltage V.sub.3 at the node N.sub.1 assuming the "H" level, the FET 3 is rendered conductive while the FET 4 is rendered non-conductive. The output signal V.sub.OUT at the node N.sub.1 begins falling at t.sub.5 when the delay time provided by the CMOS inverter I.sub.2 has lapsed after the voltage V.sub.3 on the node N.sub.1 shifted up to the "H" level. At t.sub.6, the output signal V.sub.OUT goes down to the "L" level.
As can be seen in FIG. 3, with the input buffer circuit shown, undesirable undershoot or ringing are caused in the output waveform as the output signal V.sub.OUT falls off during the time interval t.sub.5 -t.sub.6. However, no overshoot and ringing are witnessed as the output signal V.sub.OUT goes up during the time interval between t.sub.2 and t.sub.3. The reason for this is as follows.
The time interval t.sub.5 -t.sub.6 during which the output signal V.sub.OUT drops from "H" level to the "L" level is relatively short, resulting in a steep downhill slope in the output waveform as shown in FIG. 3. On the other hand, the time interval t.sub.2 -t.sub.3 during which the output signal V.sub.OUT rises from the "L" level to the "H" level is relatively long, forming a gentle uphill slope in the output waveform. The rise and fall times of the output waveform are determined by the time it takes for the output capacitance C.sub.o (including a stray capacitance of the inverter and an input capacitance of an external circuit connected to receive the V.sub.OUT) to be charged and discharged. The charging and discharging times of the output capacitance C.sub.o is proportional to the product of the value of the output capacitance C.sub.o and the on-resistance of the the FETs 3 or 4. Assuming that the output capacitance is fixed, the rise time t.sub.2 -t.sub.3 and the fall time t.sub.5 -t.sub.6 of the CMOS inverter I.sub.2 is determined by the on-resistances of the FETs 3 and 4. It should be noted here that, the transistor size being the same, the on-resistance of the FET 3 is larger than that of the FET 4. This is because the high P-channel FET 3 has a small mobility than the N-channel FET 4.
Due to the above-mentioned fact that the on-resistance for the P-channel FET 3 is larger than that of the N-channel FET 4, the charging time (equal to t.sub.2 -t.sub.3 of FIG. 3) of the output capacitance C.sub.o by the output signal V.sub.OUT rising from the "L" level to the "H" level is longer than the fall time t.sub.5 -t.sub.6 of the output signal V.sub.OUT or the discharge time of the output capacitor C.sub.o where the output voltage VF.sub.OUT drops from the "H" level to the "L" level. In short, the rise time of the output signal V.sub.OUT is longer than the fall time of the output signal. Phrased differently, the output signal V.sub.OUT increases gradually and gently and decreases rapidly and sharply.
Connected to the output of the output buffer is inductance included in the package and the external electrical interconnections as well as the above stated output capacitance C.sub.o. Since the impedance of the input buffer is not matched with the external impedance, undershoot and ringing are caused in the output waveform as the output signal V.sub.OUT drops to the "L" level. The undershoot and ringing in turn lead to an erroneous operation of externally connected devices.
The IC device 10 having the input buffer circuit 12 of FIG. 1 incorporate therein tends to suffer some problems when put to test procedures. For example, components used to connect the IC device to the IC tester such as IC sockets and the performance board as well as the electrical interconnections within the tester have their own distributed inductances as indicated by the reference numeral 14, 21 and 31 in FIG. 1. These inductances bring about a change in the supply voltage in the IC tester 30 whenever the supply current undergoes a transient change. On the other hand, the logic level of the inputs supplied from the IC tester into the IC device is determined based on the common ground potential GND as a reference voltage. Thus, if the fluctuating supply voltage V.sub.DD and GND in the IC tester 30 are transferred into the IC device, the threshold values of the P- and N-channel FETs 1-4 are caused to shift, giving rise to the aforementioned undershoot and ringing. This in turn disturbs the normal test procedures of the IC device.
One prior art of particular interest to this invention is disclosed in a paper by T. Wong et al. entitled, "A High Performance 129k Gate MOS Array". The paper describes two pairs of P- and N-channel MOSFETs which are connected in series between a supply voltage and a ground potential.